Sattiwk Mitra

S. Mitra

Verified Expert

Analog & RF IC Design Engineer

  • VLSI
  • Cadence
  • Semiconductor Circuit Design Expert
  • VLSI Design
  • Analog Electronics
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18 ordersMember since 2018

I am an Analog and RF IC Design Engineer and Project Lead specializing in high-speed, high-performance circuit design across advanced FinFET technologies. My experience spans TSMC 2nm, 3nm, 7nm, 16nm, 28nm, 65nm, and Samsung 8nm, with expertise in high-speed SerDes, line drivers, LNAs, mixers, DACs, DLLs, LDOs, bandgap references, clocking circuits, and UCIe interfaces. Over the past few years, I have progressed from designing circuit blocks to owning complete IPs end-to-end, covering architecture, design, verification, layout guidance, post-layout optimization, AMS sign-off, silicon validation, and customer delivery. As Project Lead, I currently lead a TSMC 2nm high-speed Line Driver, a TSMC 3nm Low Noise Amplifier (LNA), and a TSMC 7nm space-grade mixed-signal DAC project. Most recently, I led the design and customer delivery of a TSMC 3nm 224 Gsps high-swing driver for an opto-electronic modulator. This project marked my first large-scale RF design, involving aggressive performance targets, advanced EM analysis, and high-speed RF layout methodologies, resulting in multiple patent filings. Highlights include driving a serializer to achieve 10 GHz post-layout operation against an 8 GHz specification, recovering 12 dB of PSRR in a production LDO through post-layout root-cause analysis, executing key blocks of a 3nm DLL—including the BBPD, TDC-based false-lock detection, deserializer, and top-level AMS verification—and developing reusable verification infrastructure that improved team productivity. I also designed UCIe PHY building blocks, including deserializers, clock dividers, Sideband TX/RX, custom standard cells, and the clocking top for a high-speed Time-Interleaved ADC across advanced technology nodes. Beyond circuit design, I enjoy mentoring engineers, collaborating across analog, digital, and layout teams, and driving projects from concept to tape-out. My work has resulted in three patent filings, successful customer deliveries, reusable design methodologies, and contributions to silicon-proven products. I am passionate about pushing the limits of high-speed analog and RF systems and welcome opportunities involving SerDes, RF front-ends, mixed-signal architectures, advanced-node design, and next-generation communication interfaces. 📚 Subjects Covered 🔬 Analog IC Design 📡 RF IC Design 💻 VLSI Design ⚡ Circuit Design & Analysis 🔌 Analog Electronics 🧩 Semiconductor Devices & FinFET Technology 🖥️ Cadence Design Tools 📊 Signals & Systems 〰️ Linear Systems ⚡ Electric Circuits 🔋 Current Electricity 💻 C Programming 🐍 Python 📐 MATLAB 🔧 Programming Fundamentals 📡 Electronic Circuit Design

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About

I am an Analog and RF IC Design Engineer and Project Lead specializing in high-speed, high-performance circuit design across advanced FinFET technologies. My experience spans TSMC 2nm, 3nm, 7nm, 16nm, 28nm, 65nm, and Samsung 8nm, with expertise in high-speed SerDes, line drivers, LNAs, mixers, DACs, DLLs, LDOs, bandgap references, clocking circuits, and UCIe interfaces.

Over the past few years, I have progressed from designing circuit blocks to owning complete IPs end-to-end, covering architecture, design, verification, layout guidance, post-layout optimization, AMS sign-off, silicon validation, and customer delivery. As Project Lead, I currently lead a TSMC 2nm high-speed Line Driver, a TSMC 3nm Low Noise Amplifier (LNA), and a TSMC 7nm space-grade mixed-signal DAC project.

Most recently, I led the design and customer delivery of a TSMC 3nm 224 Gsps high-swing driver for an opto-electronic modulator. This project marked my first large-scale RF design, involving aggressive performance targets, advanced EM analysis, and high-speed RF layout methodologies, resulting in multiple patent filings.

Highlights include driving a serializer to achieve 10 GHz post-layout operation against an 8 GHz specification, recovering 12 dB of PSRR in a production LDO through post-layout root-cause analysis, executing key blocks of a 3nm DLL—including the BBPD, TDC-based false-lock detection, deserializer, and top-level AMS verification—and developing reusable verification infrastructure that improved team productivity. I also designed UCIe PHY building blocks, including deserializers, clock dividers, Sideband TX/RX, custom standard cells, and the clocking top for a high-speed Time-Interleaved ADC across advanced technology nodes.

Beyond circuit design, I enjoy mentoring engineers, collaborating across analog, digital, and layout teams, and driving projects from concept to tape-out. My work has resulted in three patent filings, successful customer deliveries, reusable design methodologies, and contributions to silicon-proven products.

I am passionate about pushing the limits of high-speed analog and RF systems and welcome opportunities involving SerDes, RF front-ends, mixed-signal architectures, advanced-node design, and next-generation communication interfaces.

📚 Subjects Covered 🔬 Analog IC Design 📡 RF IC Design 💻 VLSI Design ⚡ Circuit Design & Analysis 🔌 Analog Electronics 🧩 Semiconductor Devices & FinFET Technology 🖥️ Cadence Design Tools 📊 Signals & Systems 〰️ Linear Systems ⚡ Electric Circuits 🔋 Current Electricity 💻 C Programming 🐍 Python 📐 MATLAB 🔧 Programming Fundamentals 📡 Electronic Circuit Design

Academic background

Qualifications

  • 🎓 Master’s Degree — VLSI/Microelectronics or exact field

Languages

English

Expertise

Specialization

Analog IC DesignRF IC DesignVLSI & Integrated Circuit DesignHigh-Speed Circuit DesignFinFET & Semiconductor TechnologiesCadence IC DesignAnalog & Mixed-Signal CircuitsCircuit Design & AnalysisRF & High-Frequency ElectronicsLow-Power Circuit DesignAdvanced Semiconductor NodesSignals & SystemsElectronic Circuit SimulationIC Design & Optimization

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Python for data science

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