Computer organisation and architecture Assignment Help & Online Tutoring

Architecture is what the programmer sees: the instruction set, registers, data types and addressing modes. Organisation is how that is implemented in hardware, including control signals, buses, cache and pipelines. Two machines can share an architecture but have different organisations and performance.

The instruction cycle is the sequence the CPU repeats: fetch the instruction from memory, decode it, execute it, and store any result. Some descriptions add an operand fetch stage. The program counter holds the address of the next instruction and is updated each cycle.

Pipelining splits instruction execution into stages so that several instructions are in progress at once, each in a different stage. It increases throughput rather than reducing the time for one instruction. Hazards can force stalls, so real speedup is lower than the number of stages.

There are three types. Structural hazards occur when two instructions need the same hardware. Data hazards occur when an instruction needs a result that is not ready. Control hazards occur after branches. They are handled with stalls, forwarding and branch prediction.

Cache is small, fast memory between the CPU and main memory that holds recently and frequently used data. It works because programs show locality of reference. By serving most accesses quickly, it cuts the average memory access time, which is one of the biggest limits on performance.

The hit ratio is the fraction of memory accesses found in cache. If 90 of 100 accesses hit, the hit ratio is 0.9 and the miss ratio is 0.1. It is used with the hit time and miss penalty to work out the average memory access time.

The three common schemes are direct mapping, fully associative and set associative. Direct mapping is simple but can cause conflicts. Fully associative is flexible but costly to search. Set associative is a compromise and is widely used in real processors, so it appears often in questions.

RISC designs use a small set of simple, fixed-length instructions that suit pipelining. CISC designs use more complex, variable-length instructions that can do more per instruction. Modern processors often combine ideas from both, so avoid presenting them as entirely separate in an answer.

The memory hierarchy arranges storage by speed, size and cost: registers, cache, main memory, then secondary storage. Faster levels are smaller and more expensive per byte. The aim is to give the illusion of memory that is both large and fast, using locality of reference.

Direct memory access lets a device transfer data to or from memory without the CPU moving each item. The CPU sets up the transfer, then the DMA controller performs it and signals completion with an interrupt. This frees the processor for other work during large transfers.

With polling, the CPU repeatedly checks whether a device is ready, which wastes cycles. With interrupts, the device signals the CPU when it is ready, so the processor can do other work meanwhile. Interrupts are more efficient but add complexity in handling and priorities.

CPI is the average number of clock cycles per instruction. It is used with the instruction count and clock rate to find CPU time. A lower CPI is better, but it must be considered with the clock rate, because designs often trade one against the other.

An addressing mode is the way an instruction specifies where its operand is. Common modes include immediate, register, direct, indirect and indexed. Different modes give flexibility in accessing arrays and structures, and exam questions often ask you to work out the effective address.

Amdahl's law states that the speedup from improving part of a system is limited by the fraction of time that part is used. If only half the execution time can be improved, the overall speedup cannot exceed two, however much that part is accelerated.

Yes. A one-to-one tutor can explain the datapath and control, work through cache, pipeline and performance calculations and check your reasoning. You complete your own assessed work in line with your university's rules. Lessons are online and follow your own course material.