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Most problems in a student PCB come from doing these out of order.

1. Specification — supply voltages, currents, interfaces, size and mounting constraints.
2. Schematic capture — the circuit as a diagram, with every part given a value and a part number.
3. Footprint assignment — each schematic symbol linked to a physical land pattern.
4. Netlist transfer to the layout tool.
5. Board outline and stackup — size, shape, mounting holes, number of layers.
6. Placement — the stage that decides whether routing will be easy or painful.
7. Routing — power first, then critical signals, then the rest.
8. Copper pours and ground — usually a solid ground plane.
9. Design rule check (DRC) and electrical rule check.
10. Manufacturing output — Gerbers, drill file, pick-and-place, bill of materials.

Placement is where the board is really designed. A well-placed board almost routes itself; a badly placed one cannot be rescued by clever routing.

The schematic defines connectivity, not physical reality. The footprint does.

The errors that actually cost a board run: - A footprint whose pad spacing does not match the real part. - The wrong package chosen for a correct part number. - Pin 1 orientation inconsistent between footprint, silkscreen and assembly. - A connector footprint mirrored, so it fits only from the wrong side.

None of these show up in simulation and none are caught by DRC. Check every footprint against the manufacturer datasheet drawing, and print the layout at 1:1 scale and place the real component on it before ordering. That five-minute check has saved more boards than any software feature.

Copper resistivity is about 1.68 × 10⁻⁸ Ω·m. Standard 1 oz copper is about 35 µm thick.

For a track 10 mm long and 0.25 mm wide in 1 oz copper:

Cross-sectional area = 0.25 × 10⁻³ m × 35 × 10⁻⁶ m = 8.75 × 10⁻⁹ m²

R = ρL ÷ A = (1.68 × 10⁻⁸ × 0.010) ÷ (8.75 × 10⁻⁹) = 0.0192 Ω

At 1 A that is a voltage drop of 19.2 mV and a power dissipation of 19.2 mW in the track.

Two ways to halve it. Double the width to 0.5 mm, or specify 2 oz copper at 70 µm. Either gives 0.0096 Ω and 9.6 mV. Width is normally the cheaper option, since heavier copper raises board cost and limits how fine the rest of the features can be.

This is why power tracks are wide and signal tracks are not: 19 mV is irrelevant on a signal line and serious on a 3.3 V rail feeding a regulator's feedback point. For current-carrying capacity and temperature rise, use the tables in the manufacturing standard your course specifies rather than a rule of thumb.

• Decoupling capacitors as close to the supply pin as possible, with the shortest path to the plane. A decoupling capacitor on the far side of the chip is decoration.
• Connectors on the board edge, oriented so cables leave sensibly.
• Keep switching sections away from sensitive analogue, and keep their current loops small.
• Crystals close to their IC, with short tracks and a local ground.
• Group by function, following the signal flow on the schematic.
• Respect mechanical constraints early: height limits, mounting holes, keep-out zones.

A practical habit: place the parts whose position is fixed first (connectors, mounting holes, anything the enclosure dictates), then the parts that must be near them, then everything else.

Route power and ground first, then the signals with the tightest constraints, then the remainder.

• A solid ground plane on its own layer is the single biggest improvement available on a two-layer or four-layer board.
• Avoid splitting the ground plane under a signal that crosses the split: the return current has to detour, which creates a loop and radiates.
• Keep high-speed tracks short and direct, with no unnecessary vias, since each via adds inductance and a stub.
• Match lengths only where the interface requires it, and say which interface demands it.
• Avoid acute angles; use 45° corners or arcs, mainly for etching consistency.
• Controlled impedance needs a defined stackup and trace geometry, so agree it with the fabricator rather than assuming defaults.

The return current question is the one that separates a considered layout from a tidy-looking one: current returns on the path of least impedance, which at high frequency is directly under the track, not the shortest route on the plane.